Typically, power management for a single processor on a single die has constituted changing global power states by altering global performance resources supplied to the single die, such as voltage and frequency. Therefore, when a processor is performing in a max performance/power state, the max voltage and frequency is supplied to the processor. To change the power state of the processor the frequency, voltage, or both are changed to effectuate the power state change. Other methods of power management have included reducing power to functional units of a microprocessor depending on whether the functional unit will be speculatively used to execute instructions in a cache, such as in co-pending application 750,256.
However, advances in semi-conductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, microprocessor configurations have evolved from a basic single processor on a single die to include multiple processor cores or multiple processor threads on a single die.
Typically, multiple threads share common data caches, instruction caches, execution units, branch predictors, control logic, bus interfaces, and other processor resources, while maintaining a unique architecture state for each processor. One example of multi-threading technology is Hyper-Threading Technology (HT) from Intel® Corporation of Santa Clara, Calif., that enables execution of threads in parallel using a signal physical processor. HT is achieved by having multiple architectural states that share one set of caches, execution units, branch predictors, control logic, and buses.
In addition, multi-core technology tends to include multiple core processors on a single die. Each core may have its own caches, execution units, branch predictors, control logic, and architecture states. Yet, each core may also share some of those processing resources, as well as other resources, such as a bus interface. Multi-threads and multi-cores tend to overlap in that any configuration of multiple processors on a single die may share some resources, while having their own separate processing resources.
In fact, it is common for an operating system to logically view a multi-core single die processor and a multi-threaded single die processor exactly the same: as multiple processors. Therefore, a single die processor with either multiple cores or multiple threads are typically referred to as a physical processor having multiple “logical processors”, wherein each logical processor may be a thread or a core. Moreover, the operating system may issue an independent power management request for any single logical processor on the physical processor, since the operating system may not differentiate between physical and logical processors.
Therefore, with the advent of logical processors the coarse-grained control of global resource power management may affect both power consumption and processor performance. As a simple example, if a physical processor has two logical processors running at a max performance power state and the operating system requests one of the two logical processors to enter a lower performance power state, then with the current global power management controls, there may be only two options. First, either the voltage or frequency may be reduced. However, since global performance resources, such as voltage and frequency, are supplied to the whole physical processor, both logical processors would be affected by the reduction instead of just the single logical processor. Second, the request for one of the processors to enter into a lower performance power state may be ignored. Yet, this would result in both logical processors operating at max performance, which may waste power. Furthermore, hardware speculation of future units to be utilized to reduce power to functional units, as mentioned above, may not allow the operating system to modify performance of individual logical processors.